The present invention relates to a sample clock recovery circuit.
In a conventional digital visual communications system, an analog image signal is sampled, converted to a digital bit stream and transmitted at a line clock rate. At the receiving end of the system, the transmitted digital signal is written into a first-in-first-out (FIFO) memory on a bit-parallel word basis and read out of the memory in response to a local sampling pulse generated by a frequency control feedback loop. The output signal of the memory is supplied to a decoder where it is decoded into analog form for reproduction of the original image. The storage level of the FIFO memory is compared with reference levels to detect when the memory is almost full or almost empty. A frequency trimming signal which represents a predetermined amount of frequency is generated in response to each of these conditions and added to or subtracted from the local sampling rate depending on these conditions to prevent the memory from being overflowed or underflowed. Under the stabilized condition, the local sampling rate is synchronized with the transmitted sampling rate.
However, if a change occurs in the transmitted sampling rate when the storage level of the memory is in the neighborhood of the almost full or almost empty condition, the local sampling rate is rapidly changed and timing instability occurs in the reproduced image.